c ha2110 - 98f ref. : dscha21102181 - 29 jun 12 1 / 10 specifications subject to change without notice united monolithic semiconductors s.a.s. bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 7 - 12ghz lna gaas monolithic microwave ic description the cha2110 - 98f is a monolithic two - stages wide band low noise amplifier circuit. it is self - biased. it is designed for military, space and telecommunication systems. the circuit is manufactured with a phemt process, 0.25m gate length, via holes through the substrate, and air bridges. it is available in chip form. main features gain and nf versus frequency main electrical characteristics tamb.= + 25c symbol parameter min typ max unit freq frequency range 7 12 ghz gain linear gain 19 db nf noise figure 1.2 db pout output power @1db comp (f=10ghz) 11 dbm s21 nf in out vd1 vd2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 15 16 17 18 19 20 21 22 23 24 25 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 nf (db) s21 (db) frequency (ghz)
cha2110 - 98f 7 - 12ghz lna ref. : dscha21102181 - 29 jun 12 2 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 electrical characteristics tamb.= +25c symbol parameter min typ max unit freq frequency range 7 12 ghz gain linear gain 19 db nf noise figure 1.2 db rl_in input return losses - 12 db rl_out output return losses - 12 db p1db output power at 1db comp (f=10ghz) 11 dbm ip3 3 rd order interception point (f=10ghz) 21 db vd drain supply voltage (self biased) 4 v id drain supply current 45 ma these values are representative of measurements on test fixture. absolute maximum ratings (1) tamb.= +25c symbol parameter values unit vd drain bias voltage 5v v id drain bias current 70 ma tj junction temperature 175 c ta operating temperature range - 40 to +85 c tstg storage temperature range - 55 to +150 c (1) operation of this device above anyone of these parameters may cause permanent damage. (2) duration < 1s. typical bias conditions tamb.= +25c symbol pad n o parameter values unit vd vd1, vd2 drain supply voltage 4 v the circuit is self - biased.
7 - 12ghz lna cha2110 - 98f ref. : dscha21102181 - 29 jun 12 3 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 test fixture measurements t=[ - 40c ; +25c ; +85c], vd = +4v, id = 45ma s21 versus frequency input return loss output return loss - 40c +25c +85c - 40c - 40c +25c +25c +85c +85c
cha2110 - 98f 7 - 12ghz lna ref. : dscha21102181 - 29 jun 12 4 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 test fixture measurements t=[ - 40c ; +25c ; +85c], vd = +4v, id = 45ma noise figure versus frequency p1db versus frequency - 40c +25c +85c +85c +25c - 40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 nf (db) frequency (ghz)
7 - 12ghz lna cha2110 - 98f ref. : dscha21102181 - 29 jun 12 5 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 test fixture measurements tamb=+25c, vd = +4v, id = 45ma ip3 versus frequency
cha2110 - 98f 7 - 12ghz lna ref. : dscha21102181 - 29 jun 12 6 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 mechanical data chip thickness: 100m. chip size: 1300x1930 35m all dimensions are in micrometers rf pads (1, 9) = 100x120m2 dc pads (2,3,4,5,6,7,8,10,11,12,13) = 100x100m2 pin number pin name description 1 e input rf 2 none nc 3, 4 gnd nc 5 none nc 6, 7 vd1 vd 8 vd2 vd 9 s output rf 10 2b nc 11 2a nc 12 1b nc 13 1a nc 1 2 3 4 5 6 7 8 9 10 11 12 13
7 - 12ghz lna cha2110 - 98f ref. : dscha21102181 - 29 jun 12 7 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended assembly plan note: supply feed should be bypassed. 25m diameter gold wire is to be preferred. recommended circuit bonding table label type decoupling comment e input rf n/a inductance (lbonding750m) = 0.6nh , 1 gold wire with diameter of 25m vd1, vd2 vd 100pf & 10nf drain supply inductance ? 1nh s output rf n/a inductance (lbonding500m) = 0.4nh , 1 gold wire with diameter of 25m 100pf 10nf vd2 vd1 100pf 10nf
cha2110 - 98f 7 - 12ghz lna ref. : dscha21102181 - 29 jun 12 8 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 chip biasing options this chip is self - biased, and flexibility is provided by the access to number of pads. the internal dc electrical schematic is given in order to use these pads in a safe way. the requirement is : not to exceed vds = 3.5volt (internal drain to source voltage). we propose three standard biasing : low noise and low consumption: vd = 4v. the pads 1a, 1b, 2a and 2b are non - connected ( nc). idd = 45ma & pout - 1db = +11dbm typical (f=10ghz). low noise and highe r gain: vd = 4v and 1a or 1b grounded. all the other pads non connected (nc). idd = 55ma & pout - 1db = +11dbm typical (f=10ghz) low noise and higher output power: vd = 4v and 2a or 2b grounded. all the other pads non connected (nc). idd = 55ma & pout - 1db = +13dbm typical (f=10ghz) vd1 gnd in out vd2 1b 1a 2 b 2 a 10 ? 15 ? 12 ? 18 ? 7 ? 5.5 ? 5.5 ? 7 ? 18 ? 2k ?
7 - 12ghz lna cha2110 - 98f ref. : dscha21102181 - 29 jun 12 9 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 note
cha2110 - 98f 7 - 12ghz lna ref. : dscha21102181 - 29 jun 12 10 / 10 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended esd management refer to the application note an0020 available at http://www.ums - gaas.com for esd sensitivity and handling recommendations for the ums products. recommended environmental management ums products are compliant with the regulation in particular with the directives rohs n2011/65 and reach n1907/2006. more environmental data a re available in the application note an0019 also available at http://www.ums - gaas.com . ordering information chip form: cha2110 - 98f /00 information furnished is believed to be accurate and reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of united monolithic semiconductors s.a.s. . specifications mentioned in thi s publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or systems without express written approval from united monolithic semiconductors s.a.s.
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